In this letter, we investigated in detail the basic characteristics of W type slab waveguide in the vicinity of the cutoff frequency. Concerning with the leaky mode, we obtained some interesting results.

High-resolution Direction-of-Arrival (DOA) estimation techniques for antenna arrays have been widely desired in many applications such as smart antennas, RF position location, and RFID system. To realize high-resolution capability of the techniques, precise array calibration is necessary. For an array of single-mode elements, a calibration matrix derived by the open-circuit method is the simplest one. Unfortunately, calibration performance of the method is not enough for the high-reslution DOA estimation techniques. In this paper, we consider problems of the calibration matrix derived by the method, and show that errors in the matrix can be effectively removed by an optimal diagonal weight coefficient. In the proposed compensation technique, the number of newly introduced parameters, or unknowns, is only one for an array of the identical elements. Performance of the simple compensation technique is verified numerically and experimentally.

Super regenerative detectors using a resonant tunneling diode (RTD) were fabricated and investigated for ultra-high frequency detectors. A key point is to use the RTD super regenerative detector for detecting much higher frequencies than the free-running oscillation frequency of the detector. This is possible owing to the superior high frequency characteristics of the RTDs. This has various advantages, such as circuit simplicity, easy design, and low power consumption. Clear detection of 50,GHz signal was demonstrated with a super regenerative detector which has 1.5,GHz free-running frequency. Moreover, detailed experiments revealed that the frequency dependence of the detection efficiency is smooth, and the harmonic frequencies have no effect. This is advantageous for high frequency detection.

We describe an approach to describe moving pictures in terms of their structural properties for video editing, video indexing, and video coding. The description contains 2D shape, motion, spatial relation, and relative depth of each region. To obtain the description, we develop the incremental segmentation scheme which includes dynamic occlusion analysis to determine relative depths of several objects. The scheme has been designed along the analysis-by-synthesis" approach, and uses a sequence of images to estimate object boundaries and motion information successively/incrementally. The scheme consists of three components: motion estimation, prediction with dynamic occlusion analysis, and update of the segmentation results. By combining the information from extended (longer) image sequences, and also by treating the segmentation and dynamic occlusion analysis simultaneously, the scheme attempts to improve successively over time the accuracy of the object boundary and motion estimation.

Application-level multicast (ALM) is a novel technology for multipoint applications, such as large scale file distribution, video and audio streaming, and video conferencing. Although many ALM mechanisms or algorithms have been proposed, all the multicast functions have been independently developed and integrated into individual applications. In such a situation, the development of ALM applications includes a lot of redundancy. Our goal is to improve the efficiency of developing ALM applications by reducing the development redundancy and to provide application developers with a middleware on which various ALM applications can be efficiently developed with minimum efforts. To this end, we develop a functional unit oriented ALM middleware, namely RelayCast. RelayCast provides a minimum but fundamental set of functionality as a functional unit, and constructs the basis on which additional and specific functions (i.e. codec, video capture, etc.) for each application are implemented. Some functional units contain several components with different algorithms, and RelayCast meets the requirements of various applications by choosing the appropriate component. In this paper, we propose RelayCast architecture, and present the implementation and experiments of a prototype.

Real-time and reliable radio communication is essential for wireless control systems (WCS). In WCS, preambles create significant overhead and affect the real-time capability since payloads are typically small. To shorten the preamble transmission time in OFDM systems, previous works have considered adopting either time-direction extrapolation (TDE) or frequency-direction interpolation (FDI) for channel estimation which however result in poor performance in fast fading channels and frequency-selective fading channels, respectively. In this work, we propose a subcarrier-selectable short preamble (SSSP) by introducing selectability to subcarrier sampling patterns of a preamble such that it can provide full sampling coverage of all subcarriers with several preamble transmissions. In addition, we introduce adaptability to a channel estimation algorithm for the SSSP so that it conforms to both fast and frequency-selective channels. Simulation results validate the feasibility of the proposed method in terms of the reliability and real-time capability. In particular, the SSSP scheme shows its advantage in flexibility as it can provide a low error rate and short communication time in various channel conditions.

This paper proposes a MAC protocol for presence information discovery in ubiquitous networks. The proposed protocol is designed for proactive discovery in which wireless devices periodically broadcast packets containing presence information. The protocol is based on Framed Aloha. The objective of the protocol is to assure the discovery time of single-hop neighbors considering wireless collisions and also power consumption. In this paper, we show that the proposed protocol is able to assure specified discovery time in distributed networks with random topology.

Burst switched WDM optical networks are coming up as suitable network architectures for future Optical Internet backbones. However, the lack of optical processing capabilities results in increased burst blocking probability, which in turn lead to very limited network performance. Efficient contention resolution algorithm is therefore necessary. In this paper, we propose a distributed wavelength assignment algorithm named Priority-based Wavelength Assignment (PWA) for such networks. Each node selectively assigns wavelengths based on the wavelength priority information "learned" from its wavelength utilization history in a distributed manner. As the learning process progresses, nodes in the same part of the network tend to assign different wavelengths to avoid contentions. Simulation results show that the PWA can effectively reduce the blocking probability and increase the performance of burst optical networks compared to previous algorithms such as random assignment.

Load size for a service on the Internet changes remarkably every hour. Thus, it is expected for service system scales to change dynamically according to load size. KVS (key-value store) is a scalable DBMS (database management system) widely used in largescale Internet services. In this paper, we focus on Cassandra, a popular open-source KVS implementation, and discuss methods for improving dynamic scaling performance. First, we evaluate node joining time, which is the time to complete adding a node to a running KVS system, and show that its bottleneck process is disk I/O. Second, we analyze disk accesses in the nodes and indicate that some heavily accessed files cause a large number of disk accesses. Third, we propose two methods for improving elasticity, which means decreasing node adding and removing time, of Cassandra. One method reduces disk accesses significantly by keeping the heavily accessed file in the page cache. The other method optimizes I/O scheduler behavior. Lastly, we evaluate elasticity of our methods. Our experimental results demonstrate that the methods can improve the scaling-up and scaling-down performance of Cassandra.

A supply voltage (VDD) independent temperature sensor circuit, which can be realized by the optimum combination of three current modes of n-MOSFETs including the subthreshold current using the feedback scheme from the temperature dependent voltage (VTD) output to the gates of three n-MOSFETs, was proposed and fabricated by a standard 1.2 µm n-well CMOS process. The circuit consists of only 17 MOSFETs without high resistors resulting in a small die area of 0.18 mm2. The temperature coefficient TC of the sensor circuit can be controlled by the channel length ratio L4/L3 of two n-MOSFETs. The average temperature sensor voltage VTS and its typical TC are 1.77 V at VDD=5.0 V (20) and 5.1 mV/ for VDD=5.01.0 V in the temperature range of -20-100 in case of L4/L3=9, respectively.

For future generation mobile networks, we expect that the mobile devices like PDAs, note PCs or any VoIP-enabled communicators will have the feature of being always switched on, ready for service, constantly reachable by the wireless Internet. In addition to high access speed, attractive real-time contents or other expected spectacular features of the future wireless Internet environment, the mobile terminals has to be very much energy-aware to enable literal untethered movement of the user. Mechanisms for network activities like maintaining location information and wireless system discovery, which require regular network access, should be energy-efficient and resource-efficient in general. Cellular systems employ the notion of passive connectivity to reduce the power consumption of idle mobile hosts. In IP based Multi-service User Terminal (MUT) that may have multiple wireless interfaces for receiving various classes of services from the network, there should be an efficient addressing of the energy consumption issue. To devise an energy-efficient scheme for simultaneous or single operation of the wireless interfaces attached to such terminals we should have comprehensive understanding of the power consumption of the devices/modules in various operational states. This paper investigates the power consumption pattern or behavior of some selected wireless interfaces that are good candidates for being part of the future of the multi-service user terminals. We propose a simple model for predicting energy consumption in a terminal attributed to the wireless network interfaces. We measured the actual consumption pattern to estimate the parameters of the model.

Magnetic immunoassays utilizing magnetic marker and high Tc superconducting quantum interference device (SQUID) have been performed. In this magnetic method, binding-reaction between an antigen and its antibody is detected by measuring the magnetic field from the magnetic marker. First, we discuss the magnetic property of the marker, and show that Fe3O4 particles with diameter of 25 nm can be used for remanence measurement. We also show a design of the SQUID for sensitive detection of the magnetic signal from the marker. Next, we developed a measurement system utilizing the SQUID and a reaction chamber with very low magnetic contamination. Finally, we conducted an experiment on the detection of the biological materials called IL8 and IgE. At present, a few atto-mol of IL8 and IgE has been detected, which shows the high sensitivity of the present method.

In this work, the metal-oxide-metal (MOM) capacitor in the scaled CMOS process has been modeled at high frequencies using an EM simulator, and its layout has been optimized. The modeled parasitic resistance consists of four components, and the modeled parasitic inductance consists of the comb inductance and many mutual inductances. Each component of the parasitic resistance and inductance show different degrees of dependence on the finger length and on the number of fingers. The substrate network parameters also have optimum points. As such, the geometric dependence of the characteristics of the MOM capacitor is investigated and the optimum layout in the constant-capacitance case is proposed by calculating the results of the model. The proposed MOM capacitor structures for 50fF at f =60GHz are L =5μm with M =3, and, L =2μm with M =5 and that for 100fF at f =30GHz are L =9μm with M =3, and L =4μm with M =5. The target process is 65-nm CMOS.

A test structure to separately measure sheet resistances of highly-doped-drain (HDD) and lightly-doped-drain (LDD) in LDD-type CMOSFETs with various gate spaces S having sub-100 nm sidewalls was proposed. From the reciprocal of source/drain-resistance R-1 versus S characteristics, the sheet resistance ρH of the high-conductive-region (HCR) corresponding to HDD and the approximate width WLC of the low-conductive-region (LCR) corresponding to LDD could be estimated. Both of ρH and WLC for p- and n-MOS devices were scarcely dependent on the gate voltage. The sidewall-width difference of 40 nm could be sufficiently detected by using the test structure with the S pitch of about 60 nm. The R-1 versus S characteristics showed the unstable resistance variations in the narrow S region less than 0.3 µm, which corresponded to the minimum S for the process used for the test device fabrication and suggested that various micro-loading effects seriously affected on the characteristics.

A test structure to separately analyze the location where the hot-carrier-induced CMOSFET reliability is determined around the center or the isolation-edge along the channel-width was proposed and fabricated. The test structure has four kinds of MOSFETs; [A] and [D] MOSFETs with a short and a long channel-length all over the channel width, respectively, [B] MOSFET with the short and the long channel-length around the center and the both isolation-edges, respectively, and [C] MOSFET with the channel-length regions vice versa to the [B] MOSFET. The time dependent changes of the threshold voltages VT, the saturation currents IS, the linear currents IL and the maximum transconductances β up to 50,000 s were measured. All data for the wide channel-width MOSFETs were almost categorized into three; [A], [B]/[C] and [D]. The [B]/[C] data were well estimated from simple theoretical discussions by the combination of [A] and [D] data, which mean that the reliabilities are nearly the same around the center or the isolation-edge for the CMOSFETs.

We have developed a digital coprocessor with a dynamically reconfigurable pipeline architecture specified for a layered neural network which executes on-chip learning. The coprocessor attains a learning speed of 18 MCUPS that is approximately twenty times that of the conventional DSP. This coprocessor obtains expansibility in the calculation through a larger multi-layer, network by means of a network decomposition and a distributed processing approach.

In this paper, we review a super-steep subthreshold slope (SS) (<1 mV/dec) body-tied (BT) silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) fabricated with 0.15 µm SOI technology and discuss the possibility of its use in ultralow voltage applications. The mechanism of the super-steep SS in the BT SOI MOSFET was investigated with technology computer-aided design simulation. The gate length/width and Si thickness optimizations promise further reductions in operation voltage, as well as improvement of the ION/IOFF ratio. In addition, we demonstrated control of the threshold voltage and hysteresis characteristics using the substrate and body bias in the BT SOI MOSFET.

A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.

A hard-type oscillator is defined as an oscillator having stable fixed points within a stable limit cycle. For resonant tunneling diode (RTD) oscillators, using hard-type configuration has a significant advantage that it can suppress spurious oscillations in a bias line. We have fabricated hard-type oscillators using an InGaAs-based RTD, and demonstrated a proper operation. Furthermore, the oscillating properties have been compared with a soft-type oscillator having a same parameters. It has been demonstrated that the same level of the phase noise can be obtained with a much smaller power consumption of approximately 1/20.